The present invention relates to a data transmission device having a master device and a slave device connected via at least one data transmission line and one clock signal line.
Data transmission devices of the type mentioned at the outset are used today in many electrical devices. The data exchange, for instance, between different electrical switching devices gains more and more importance.
Information on programs and functions to be executed and on the devices themselves or on current device states are to be interrogatable at any time by any device at any place, and to be exchangeable among the devices. To this end, the devices are equipped down to the lowest functional levels with intelligence and corresponding device interfaces for the data exchange.
In the low-cost area, it is preferred to use serial data transmission types. This has the advantage that fewer signal lines are needed than in the case of a parallel data transmission. To keep the outlay of required hardware as low as possible, the data transmission should be implemented synchronously.
A serial synchronous data transmission between two stations requires at least one data line for bidirectional data transmission and one clock signal line or two data lines for unidirectional data transmission and one clock signal line. The clock signal line, which controls the entire signal flow between the stations, is of particular importance here. This clock signal is generated by a master device. A slave device which communicates with the master device has to adapt itself to this predetermined clock.
Known interfaces for these serial synchronous transmission types include: I2C (Philips), SPI (Motorola), Microwire (National Semiconductor), or the like. These interfaces are generally used for the data transmission between different components within one device.
If the intention is to implement such a serial synchronous data transmission between individual devices, measures have to be taken with respect to possibly occurring interference signals. To protect, in particular, the clock signal line from interference effects, provision is usually made for hardware interference suppression measures in the form of filters and screenings. In some cases, the interference immunity is supported by additional software interference suppression measures. Such software interference suppression measures are generally implemented via a repeated reading of the received information. To this end, the information is repeatedly read at intervals of about 5 to 20 μs (average duration of the interference effects) and evaluated via a majority decision (signals which are read in the majority of cases are rated as correct). To increase the interference immunity in this kind of interference suppression, the number of read operations is increased.
Interference suppression via hardware involves the disadvantage of a relatively large expenditure for hardware. Furthermore, digital software interference suppression is insufficient since only the master device which, in fact, generates the clock signal, is able to perform repeated read operations by delaying or halting the clock signal for the required (check) read time.